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(R)
September 2000
Features
CT UCT OD U R OD E PR ITUTE P nter at T e T OLE OBS LE SUBS upport C om/tsc IB l S tersil.c SS ica .in w A PO echn FOR act our T IL or ww 8-Bit, nt RS E co 8-INT 1-88
HI1396
125 MSPS, Flash A/D Converter
Description
The HI1396 is an 8-bit, ultra high speed flash analog-to-digital converter IC capable of digitizing analog signals at the maximum rate of 125 MSPS. The digital I/O levels of the converter are compatible with ECL 100K/10KH/10K.
* Differential Linearity Error 0.5 LSB (Typ) or Less * Integral Linearity Error 0.5 LSB (Typ) or Less * Built-In Integral Linearity Compensation Circuit * Ultra High Speed Operation with Maximum Conversion Rate of 125 MSPS (Min) * Low Input Capacitance (Typ) . . . . . . . . . . . . . . . . . 18pF * Wide Analog Input Bandwidth (Min for Full Scale Input) . . . . . . . . . . . . . . . . . . 200MHz * Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . -5.2V * Low Power Consumption (Typ) . . . . . . . . . . . . . 870mW * Low Error Rate * Operable at 50% Clock Duty Cycle * Capable of Driving 50 Loads * Direct Replacement for Sony CXA1396
Part Number Information
PART NUMBER HI1396JCJ HI1396AIL TEMP. RANGE (oC) -20 to 75 -20 to 100 PACKAGE 42 Ld SBDIP 68 Ld CLCC PKG. NO. D42.6 J68.A
Applications
* Video Digitizing * HDTV (High Definition TV) * Communication Systems * Radar Systems
* Direct RF Down-Conversion * Digital Oscilloscopes
Pinouts
HI1396 (SBDIP) TOP VIEW
NC NC NC AVEE 1 NC LINV DVEE DGND1 DGND2 (LSB) D0 D1 D2 2 3 4 5 6 7 8 9 42 NC 41 VRT 40 NC 39 AVEE 38 AVEE 37 NC 36 NC 35 AGND 34 VIN 33 AGND 32 VRM 31 AGND 30 VIN 29 AGND 28 NC 27 NC 26 AVEE 25 AVEE 24 NC 23 VRB 22 NC NC AVEE AVEE NC VRT NC AVEE NC NC NC LINV NC DVEE NC DGND1 DGND2 NC
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
HI1396 (CLCC) TOP VIEW
NC NC AGND VIN AGND VRM AGND AGND NC VIN NC NC NC NC
60 NC 59 AVEE 58 AVEE 57 NC 56 VRB 55 NC 54 NC 53 NC 52 CLK 51 CLK 50 NC 49 MINV 48 NC 47 DVEE 46 NC 45 NC 44 NC
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
D3 10 D4 11 D5 12 D6 13 (MSB) D7 14 DGND2 15 DGND2 16 DVEE 17 MINV 18 NC 19 CLK 20 CLK 21
NC NC (LSB) D0
D1 D2 D3 D4 D5
D6
(MSB) D7 NC
DGND2 DGND1 NC
NC NC
NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved
File Number
3576.4
1
HI1396 Functional Block Diagram
MINV VRT R1 COMPARATOR R/2 R 1 R D7 (MSB) 2 R D6 63 R VIN 64 R 65 OUTPUT D3 R 126 R R2 R 128 R 129 D0 (LSB) 127 ENCODE LOGIC D1 D2 D4 D5
VRM
R 191 R VIN 192 R 193
R 254 R 255 VRB CLK CLK R3 R/2
CLOCK DRIVER LINV
2
HI1396
Electrical Specifications
PARAMETER SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL HI1396JCJ, HI1396AIL Differential Linearity Error, DNL HI1396JCJ, HI1396AIL ANALOG INPUT Input Bandwidth Analog Input Capacitance, CIN Analog Input Resistance, RIN Input Bias Current, IIN REFERENCE INPUTS Reference Resistance, RREF Offset Voltage EOT EOB DIGITAL INPUTS Logic H Level, VIH Logic L Level, VIL Logic H Current, IIH Logic L Current, IIL Input Capacitance DIGITAL OUTPUTS Logic H Level, VOH Logic L Level, VOL TIMING CHARACTERISTICS Output Rise Time, tr Output Fall Time, tf Output Delay, tOD H Pulse Width of Clock, tPW1 L Pulse Width of Clock, tPW0 DYNAMIC CHARACTERISTICS Maximum Conversion Rate, fC Aperture Jitter, tAJ Sampling Delay, tDS Signal to Noise Ratio (SINAD) RMS Signal = ----------------------------------------------------------------RMS Noise + Distortion Error Rate Differential Gain Error, DG Differential Phase Error, DP POWER SUPPLY CHARACTERISTICS Supply Current, IEE Power Consumption Note 3 -230 -160 870 mA mW Input = 1MHz, Full Scale fC = 125 MSPS Input = 31.5MHz, Full Scale fC = 125 MSPS Input = 31.249MHz, Full Scale Error > 16 LSB, fC = 125 MSPS NTSC 40 IRE Mod. Ramp, fC = 125 MSPS Error Rate 10-9 TPS (Note 2) 125 10 1.5 46 40 1.0 0.5 10-9 MSPS ps ns dB dB TPS (Note 2) % Degree RL = 50 to -2V, 20% to 80% RL = 50 to -2V, 20% to 80% 0.5 0.5 3.0 4.0 4.0 0.9 1.0 3.6 1.2 1.3 4.2 ns ns ns ns ns RL = 50 to -2V RL = 50 to -2V -1.10 -1.62 V V Input Connected to -0.8V Input Connected to -1.6V -1.13 0 0 7 -1.50 50 50 V V A A pF VRT VRB 8 0 19 15 32 24 mV mV 75 110 155 VIN = -1V VIN = 2VP-P VIN = 1V + 0.07VRMS 200 50 20 17 190 130 400 MHz pF k A fC = 125 MSPS 0.5 LSB fC = 125 MSPS 0.3 0.5 LSB 8 Bits TA = 25oC, AVEE = DVEE = -5.2V, VRT = 0V, VRB = -2V (Note 1) TEST CONDITIONS MIN TYP MAX UNIT
3
HI1396
Electrical Specifications
PARAMETER NOTES: 1. Electrical Specifications guaranteed within stated operating conditions. 2. TPS: Times Per Sample. 3. ( V RT - V RB ) PD = IEE * V EE + -----------------------------------R REF
2
TA = 25oC, AVEE = DVEE = -5.2V, VRT = 0V, VRB = -2V (Note 1) (Continued) TEST CONDITIONS MIN TYP MAX UNIT
4. TA specified in still air and without heat sink. To extend temperature range, appropriate heat management techniques must be employed.
Timing Diagram
N+1 N+2 tPW1 CLK CLK tPW0
ANALOG IN
N
DIGITAL OUT tOD
N-1
20%
80% tr
N
20%
N+1 80% tf
FIGURE 1.
Pin Descriptions and I/O Pin Equivalent Circuits
PIN NUMBER DIP 29, 31, 33, 35 LCC 49, 51, 53, 55 SYMBOL AGND I/O STANDARD VOLTAGE LEVEL 0V
EQUIVALENT CIRCUIT
DESCRIPTION Analog GND. Used as GND for input buffers and latches of comparators. Isolated from DGND1, DGND2. Analog VEE -5.2V (Typ). Internally connected to DV EE (Resistance: 4 to 6). Bypass with 0.1F to AGND.
1, 25, 26, 38, 39
41, 42, 62, 63, 67
AV EE
-
-5.2V
4
HI1396 Pin Descriptions and I/O Pin Equivalent Circuits
PIN NUMBER DIP 21 20 LCC 35 34 SYMBOL CLK CLK
R R CLK CLK R R
(Continued)
I/O I
STANDARD VOLTAGE LEVEL ECL
DGND1
EQUIVALENT CIRCUIT
DESCRIPTION CLK Input. Input complementary to CLK. When left open pulled down to -1.3V. Device is operable without CLK input, but use of complementary inputs of CLK and CLK is recommended to obtain stable high speed operation.
DVEE
R
R
5, 16 6, 15 4, 17
7, 24 8, 23 5, 30
DGND1 DGND2 DV EE
-
0V 0V -5.2V
Digital GND for internal circuits. Digital GND for output transistors. Digital VEE . Internally connected to AVEE (resistance: 4 to 6). Bypass with 0.1F to DGND
DGND2
7
14
D0
O
ECL
LSB of data outputs. External pull-down resistor is required. Data outputs. External pull-down resistors are required.
8 9 10 11 12 13 14
15 16 17 18 19 20 21
D1 D2 D3 D4 D5 D6 D7
DVEE DI
MSB of data outputs. External pull-down resistor is required.
5
HI1396 Pin Descriptions and I/O Pin Equivalent Circuits
PIN NUMBER DIP 3 LCC 3 SYMBOL LINV I/O I STANDARD VOLTAGE LEVEL ECL (Continued)
EQUIVALENT CIRCUIT
DGND1
DESCRIPTION Input pin for D0 (LSB) to D6 output polarity inversion (see A/D Output Code Table). Pulled low when left open.
18
32
MINV
I
ECL
R R LINV OR MINV R -1.3V
Input pin for D7 (MSB) output polarity inversion (see A/D Output Code Table). Pulled low when left open.
DVEE
R
30, 34
50, 54
V IN
I
VRT to VRB
AGND
Analog input pins. These two pins must be connected externally, since they are not internally connected.
VIN VIN
AVEE
23
39
VRB
I
-2V
VRT
R1 R/2
Reference voltage (bottom). Typically -2V. Bypass with a 0.1F and 10F to AGND. Reference voltage mid point. Can be used as a pin for integral linearity compensation. Reference voltage (top) typically 0V. When a voltage different from AGND is applied to this pin, bypass with a 0.1F and 10F to AGND.
32 41
52 65
VRM V RT
I I
VRB/2 0V
R COMPARATOR 1 R COMPARATOR 2 R VRM R2 R COMPARATOR 128 R COMPARATOR 129 R COMPARATOR 130 R COMPARATOR 255 VRB R3 R/2 COMPARATOR 127
6
HI1396 Pin Descriptions and I/O Pin Equivalent Circuits
PIN NUMBER DIP 2, 19, 22, 24, 27, 28, 36, 37, 40, 42 LCC 1, 2, 4, 6, 9-13, 25-29, 31, 33, 36-38, 40, 43-48, 56-61, 64, 66, 68 SYMBOL NC I/O STANDARD VOLTAGE LEVEL (Continued)
EQUIVALENT CIRCUIT
DESCRIPTION Unused pins. No internal connections have been made to these pins. Connecting them to AGND or DGND on PC board is recommended.
A/D OUTPUT CODE TABLE MINV 1, LINV 1 VIN (Note 5) 0V 0 1 STEP D7 D0 D7 0, 1 D0 D7 1, 0 D0 D7 0, 0 D0
000 * * * * * 00 000 * * * * * 00 000 * * * * * 01 * * *
100 * * * * * 00 100 * * * * * 00 100 * * * * * 01 * * * 111 * * * * * 11 000 * * * * * 00 * * * 011 * * * * * 10 011 * * * * * 11 011 * * * * * 11
011 * * * * * 11 011 * * * * * 11 011 * * * * * 10 * * * 000 * * * * * 00 111 * * * * * 11 * * * 100 * * * * * 01 100 * * * * * 00 100 * * * * * 00
111 * * * * * 11 111 * * * * * 11 111 * * * * * 10 * * * 100 * * * * * 00 011 * * * * * 11 * * * 000 * * * * * 01 000 * * * * * 00 000 * * * * * 00
-1V
127 128
011 * * * * * 11 100 * * * * * 00 * * *
254 255 -2V NOTE: 5. VRT = 0V, VRB = -2V.
111 * * * * * 10 111 * * * * * 11 111 * * * * * 11
Test Circuits
SIGNAL SOURCE fCLK 4 -1kHz VIN HI1396 CLK CLK + ECL LATCH 8 ECL LATCH A B COMPARATOR A>B PULSE COUNTER
2VP-P SINEWAVE DATA 16 SIGNAL SOURCE fCLK fCLK/4
FIGURE 2. MAXIMUM CONVERSION RATE TEST CIRCUIT
7
Test Circuits
(Continued)
HI20201 AMP VIN DUT HI1396 CLK NTSC SIGNAL SOURCE CLK 8 ECL LATCH 8 10 BIT D/A
SG (CW) 50 VBB
DELAY
VECTOR SCOPE DG/DP
FIGURE 3. DIFFERENTIAL GAIN AND PHASE ERROR TEST CIRCUIT
+V
S2
+ S1
S1 : A < B : ON S2 : A > B : ON
-V AB 8 COMPARATOR A8 A1 A0 B8 B1 B0 BUFFER
DVM CLK (125 MSPS)
"0"
"1" 8 00000000 TO 11111110
CONTROLLER
FIGURE 4. INTEGRAL AND DIFFERENTIAL LINEARITY ERROR TEST CIRCUIT
8
Test Circuits
(Continued)
IIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 HI1396JCJ 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 -2V A I EE -5.2V -1V A IIN 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 A
-1V -2V
HI1396AIL
A IEE -5.2V
FIGURE 5A.
FIGURE 5B.
FIGURE 5. ANALOG INPUT BIAS AND POWER SUPPLY CURRENT TEST CIRCUITS
VIN 67.5MHz OSC1 : VARIABLE fR AMP CLK VIN HI1396 CLK OSC2 67.5MHz ECL BUFFER 8 LOGIC ANALYZER VIN 1024 SAMPLES 0V -1V -2V
t
t
129 128 127 126 125
(LSB)
CLK
APERTURE JITTER
Aperture jitter is defined as follows:

256 tAJ = ------ = --------- x 2f 2 t

Where (unit: LSB) is the deviation of the output codes when the input frequency is exactly the same as the clock and is sampled at the largest slew rate point. FIGURE 6A. FIGURE 6B. APERTURE JITTER TEST METHOD FIGURE 6. SAMPLING DELAY AND APERTURE JITTER TEST CIRCUIT
9
HI1396
10

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